//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
// Project    : Virtex-6 Integrated Block for PCI Express
// File       : board.v
// Version    : 2.4
// Description:  Top level testbench
//
//------------------------------------------------------------------------------

`timescale 1ps/1ps

module board;

parameter          REF_CLK_FREQ                 = 0;      // 0 - 100 MHz, 1 - 125 MHz,  2 - 250 MHz

localparam         REF_CLK_HALF_CYCLE = (REF_CLK_FREQ == 0) ? 5000 :
                                        (REF_CLK_FREQ == 1) ? 4000 :
                                        (REF_CLK_FREQ == 2) ? 2000 : 0;
integer            i;

reg SYS_CLK;
reg SYS_RST;
reg PCIE_CLK;
reg PCIE_RST;

  initial
  begin
    SYS_CLK = 1'b1;
    PCIE_CLK = 1'b1;
  end

  always #2500 SYS_CLK = ~SYS_CLK;
  always #5000 PCIE_CLK = ~PCIE_CLK;
  
  wire  [3:0]  DNn;
  wire  [3:0]  DNp;
  wire  [3:0]  UPn;
  wire  [3:0]  UPp;

  InSight #(
    .SIMULATION("TRUE"),
    .LANES(4)
  ) dut(
    // SYS Inteface
    .SYS_CLKp (SYS_CLK),
    .SYS_CLKn (~SYS_CLK),
    .SYS_RST  (SYS_RST),

    // PCI-Express Interface
    .PCIE_REFCLKp(PCIE_CLK),
    .PCIE_REFCLKn(~PCIE_CLK),
    .PCIE_PERSTn(~PCIE_RST),
  
    .PCIE_RXP(DNp),
    .PCIE_RXN(DNn),
    .PCIE_TXP(UPp),
    .PCIE_TXN(UPn)
);

//
// PCI-Express Model Root Port Instance
//

  xilinx_pcie_2_0_rport_v6 # (
    .REF_CLK_FREQ(0),
    .PL_FAST_TRAIN("TRUE"),
    .LINK_CAP_MAX_LINK_WIDTH(6'h04),
    .DEVICE_ID(16'h6024),
    .ALLOW_X8_GEN2("FALSE"),
    .LINK_CAP_MAX_LINK_SPEED(4'h2),
    .LINK_CTRL2_TARGET_LINK_SPEED(4'h2),
    .DEV_CAP_MAX_PAYLOAD_SUPPORTED(3'h2),
    .VC0_TX_LASTPACKET(29),
    .VC0_RX_RAM_LIMIT(13'h7FF),
    .VC0_CPL_INFINITE("TRUE"),
    .VC0_TOTAL_CREDITS_PD(308),
    .VC0_TOTAL_CREDITS_CD(308),
    .USER_CLK_FREQ(3)
  )RP(
      // SYS Inteface
      .sys_clk(PCIE_CLK),
      .sys_reset_n(~PCIE_RST),

      // PCI-Express Interface
      .pci_exp_txn(DNn),
      .pci_exp_txp(DNp),
      .pci_exp_rxn(UPn),
      .pci_exp_rxp(UPp)
  );

  initial 
  begin
    $display("[%t] : System Reset Asserted...", $realtime);
    SYS_RST = 1'b1;
    PCIE_RST = 1'b1;
    for (i = 0; i < 500; i = i + 1)
      @(posedge PCIE_CLK);
    $display("[%t] : System Reset De-asserted...", $realtime);
    SYS_RST = 1'b0;
    PCIE_RST = 1'b0;
  end

initial begin

  if ($test$plusargs ("dump_all")) begin

`ifdef NCV // Cadence TRN dump

    $recordsetup("design=board",
                 "compress",
                 "wrapsize=100M",
                 "version=1",
                 "run=1");
    $recordvars();

`elsif VCS //Synopsys VPD dump

    $vcdplusfile("board.vpd");
    $vcdpluson;
    $vcdplusglitchon;
    $vcdplusflush;

`else

    // Verilog VC dump
    $dumpfile("board.vcd");
    $dumpvars(0, board);

`endif

  end

end


endmodule // BOARD
